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data sheet ics853s011bgi revision a may 12, 2010 1 ?2010 integrated device technology, inc. low skew, 1-to-2, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer ics853s011bi general description the ics853s011bi is a low skew, high performance 1-to-2 differential-to-2.5 v/3.3v lvpecl/ecl fanout buffer. the ics853s011bi is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics853s011bi ideal for those clock distribution applications demanding well defined performance and repeatability. features ? two differential 2.5v, 3.3v lvpecl/ecl outputs ? one differential pclk, npclk input pair ? pclk, npclk pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: >2.5ghz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on npclk input ? output skew: 5ps (typical) ? part-to-part skew: 130ps (maximum) ? propagation delay: 355ps (maximum) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.8v to -2.375v ? -40c to 85c ambient operating temperature ? available lead-free (rohs 6) package hiperclocks? ic s q0 nq0 q1 nq1 pclk npclk pulldown pullup/pulldown ics853s011bi 8-lead soic, 150mil 3.90mm x 4.90mm x 1.37 mm package body m package top view 8-lead tssop, 118mil 3.0mm x 3.0mm x 0.97 mm package body g package top view pin assignment block diagram 1 2 3 4 8 7 6 5 q0 nq0 q1 nq1 v cc pclk npcl k v ee
ics853s011bgi revision a may 12, 2010 2 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output differential output pair. lvpecl/ec l interface levels. 3, 4 q1, nq1 output differential output pair. lvpecl/ec l interface levels. 5v ee power negative supply pin. 6npclkinput pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 7 pclk input pulldown non-inverting differential l vpecl clock input. 8v cc power positive supply pin. symbol parameter test conditio ns minimum typi cal maximum units r pulldown input pulldown resistor 75 k ? r vcc/2 rpullup/pulldown resistors 50 k ?
ics853s011bgi revision a may 12, 2010 3 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v (lvpecl mode, v ee = 0v) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0v) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee ? 0.5v outputs, i o continuos current surge current 50ma 100ma operating temperature range, t a -40 c to +85 c package thermal impedance, ja (junction-to-ambie nt) for 8 lead soic 102 c/w (0 mps) package thermal impedance, ja (junction-to-ambient) for 8 lead tssop 145.4 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.8 v i ee power supply current 25 ma
ics853s011bgi revision a may 12, 2010 4 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 3b. lvpecl dc characteristics, v cc = 3.3v; v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: common mode voltage is defined as v ih . table 3c. lvpecl dc characteristics, v cc = 2.5v; v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: common mode voltage is defined as v ih . symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 2.245 2.350 2.450 2.265 2.340 2.415 2.245 2.320 2.395 v v ol output low voltage; note 1 1.380 1. 520 1.660 1.415 1.510 1.605 1.405 1.500 1.595 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 mv v cmr input high voltage common mode range; note 2 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current pclk, npclk 200 200 200 a i il input low current pclk -10 -10 -10 a npclk -200 -200 -200 a symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 1.445 1.550 1.650 1.405 1.540 1.615 1.445 1.520 1.595 v v ol output low voltage; note 1 0.580 0. 720 0.860 0.615 0.710 0.805 0.605 0.700 0.795 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 mv v cmr input high voltage common mode range; note 2 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current pclk, npclk 200 200 200 a i il input low current pclk -10 -10 -10 a npclk -200 -200 -200 a
ics853s011bgi revision a may 12, 2010 5 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 3d. ecl dc characteristics, v cc = 0v; v ee = -3.8v to -2.375v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.925v to -0.5v. note 1: outputs terminated with 50 ? to v cco ? 2v. note 2: common mode voltage is defined as v ih . symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 -1.055 -0.950 -0.850 -1.035 -0.9 60 -0.885 -1.055 -0.980 0.905 v v ol output low voltage; note 1 - 1.920 -1.780 -1.640 -1.885 -1.790 -1.695 -1.895 -1.800 -1.705 v v pp peak-to-peak input voltage 150 800 1200 150 800 1200 150 800 1200 mv v cmr input high voltage common mode range; note 2 v ee +1.2 0 v ee +1.2 0 v ee +1.2 0 v i ih input high current pclk, npclk 200 200 200 a i il input low current pclk -10 -10 -10 a npclk -200 -200 -200 a
ics853s011bgi revision a may 12, 2010 6 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer ac electrical characteristics table 4. ac characteristics, v cc = -3.8v to -2.375v or , v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at f 1.7ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the ou tputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter -40c 25c 85c units min typ max min typ max min typ max f max output frequency >2.5 >2.5 >2.5 ghz t pd propagation delay; note 1 195 330 210 340 215 355 ps t sk(o) output skew; note 2, 4 5 20 5 20 5 20 ps t sk(pp) part-to-part skew; note 3, 4 130 130 130 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 0.026 0.026 0.026 ps t r / t f output rise/fall time 20% to 80% 70 250 80 250 90 250 ps odc output duty cycle; f 750mhz 48 50 52 48 50 52 48 50 52 %
ics853s011bgi revision a may 12, 2010 7 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.026ps (typical) ssb phase noise dbc/hz offset from carr ier frequency (hz)
ics853s011bgi revision a may 12, 2010 8 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer parameter measureme nt information lvpecl output load ac test circuit part-to-part skew output rise/fall time differential input level output skew propagation delay scope qx nqx lvpecl v ee v cc, 2v -1.8v to -0.375v v cco t sk(pp) part 1 part 2 nqx qx nqy qy 20% 80% 80% 20% t r t f v swing nq0, nq1 q0, q1 v cc v ee v cmr cross points v pp npclk pclk t sk(o) nqx qx nqy qy t pd nq0, nq1 q0, q1 npclk pclk
ics853s011bgi revision a may 12, 2010 9 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer parameter measurement in formation, continued output duty cycle/pulse width/period t pw t period t pw t period odc = x 100% nq0, nq1 q0, q1
ics853s011bgi revision a may 12, 2010 10 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer application information recommendations for un used output pins outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requ ires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ics853s011bgi revision a may 12, 2010 11 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer lvpecl clock input interface the pclk /npclk accepts lvpec l, lvds, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by an sstl driver figure 2b. pclk/npclk input driven by a built-in pullup cml driver figure 2d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 2f. pclk/npclk input driven by a 3.3v lvds driver pclk npclk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk lvpecl input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ? 3.3v r1 100 ? cml built-in pullup pclk npclk 3.3v lvpecl input zo = 50 ? zo = 50 ? r1 50 ? r2 50 ? r5 100 ? - 200 ? r6 100 ? - 200 ? pclk vbb npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v lvpecl input c1 c2 pclk npclk vbb 3.3v lvpecl input r1 1k r2 1k 3.3v zo = 50 ? zo = 50 ? c1 c2 r5 100 ? lvds c3 0.1f
ics853s011bgi revision a may 12, 2010 12 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics853s011bgi revision a may 12, 2010 13 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 ? r3 250 ? r2 62.5 ? r4 62.5 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? r3 18 ? + ?
ics853s011bgi revision a may 12, 2010 14 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer power considerations this section provides information on power dissipa tion and junction temperature for the ics853s011bi. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics853s011bi is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.8v * 25ma = 95mw power (outputs) max = 29.86mw/loaded output pair if all outputs are loaded, the total power is 2 * 29.86mw = 59.72mw total power_ max (3.3v, with all outputs switching) = 95mw + 59.72mw = 154.72mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 145.4c/w per table 5a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.155w * 145.4c/w = 107.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 5a. thermal resitance ja for 8 lead tssop, forced convection table 5a. thermal resitance ja for 8 lead soic, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 145.4c/w 141.3c/w 139.3c/w ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 102.0c/w 95.0c/w 90.6c/w
ics853s011bgi revision a may 12, 2010 15 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3. calculations and equations. the purpose of this section is to derive the power dissipation for th e lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 5. figure 5. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.905v (v cc_max ? v oh_max ) = 0.905v for logic low, v out = v ol_max = v cc_max ? 1.705v (v cc_max ? v ol_max ) = 1.705v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.905v)/50 ? ] * 0.905v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.705v)/50 ? ] * 1.705v = 10.06mw total power dissipation per output pair = pd_h + pd_l = 29.86mw v out v cc v cc - 2v q1 rl 50
ics853s011bgi revision a may 12, 2010 16 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer reliability information table 6a. ja vs. air flow table for a 8 lead tssop table 6b. ja vs. air flow table for a 8 lead soic transistor count the transistor count for ics853s011bi is: 208 this device is pin compatible with and is the suggested replacement for the 853011b and 853011c. ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 145.4c/w 1 41.3c/w 139.3c/w ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 102.0c/w 95.0c/w 90.6c/w
ics853s011bgi revision a may 12, 2010 17 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer package outlines an d package dimensions package outline - g suffix for 8 lead tssop table 7a. package dimensions reference document: jedec publication 95, mo-187 package outline - m suffix for 8 lead soic table 7b. package dimensions reference document: jedec publication 95, ms-012 all dimensions in millimeters symbol minimum maximum n 8 a 1.10 a1 00.15 a2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 d 3.00 basic e 4.90 basic e1 3.00 basic e 0.65 basic e1 1.95 basic l 0.40 0.80 0 8 aaa 0.10 a 2 all dimensions in millimeters symbol minimum maximum n 8 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 0 8
ics853s011bgi revision a may 12, 2010 18 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer ordering information table 8. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configur ation and are rohs compliant. part/order number marking package shipping packaging temperature 853S011BMILF 3s011bil ?lead free? 8 lead soic tube -40 c to 85 c 853S011BMILFt 3s011bil ?lead free? 8 lead soic 2500 tape & reel -40 c to 85 c 853s011bgilf 1bil ?lead free? 8 lead tssop tube -40 c to 85 c 853s011bgilft 1bil ?lead free? 8 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics853s011bgi revision a may 12, 2010 19 ?2010 integrated device technology, inc. ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer revision history sheet rev table page description of change date t3b - t3d t8 4, 5 10 18 lvpecl/ecl dc characteristics t ables - updated notes. corrected v pp unit from v to mv. updated ?wiring the different ial input to accept single-ended levels? section. ordering information table - corrected tssop marking. 5/12/10
ics853s011bi data sheet low skew, 1-to-2, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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